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1/4 inch vga cmos im age sensor s5k433ca, s5k433la 1 s5k433ca, s5k433la ( 1/4? vga cmos image sensor ) preliminary specification revision 0.3 .1 july 2002
s5k433ca, s5k433la 1/4 ? vga cmos image sens or 2 document title 1/4? optical size 640x480(vga) 3.3v/2.8v cmos image sensor revision history revision no. history draft date remark 0.0 initial draft feb. 16 , 200 2 preliminary 0.1 pin description error corrected (lhold polarity). feb. 21, 2002 preliminary timing chart added. 0.2 strb signal polarity error corrected apr. 10, 2002 preliminary sfcm timing diagram corrected operation description added. 0.3 dc timing characteristics specification changed july 8, 2002 preliminary ac timing characteristics specification changed strb and lhold pin s are deleted 0.3.1 minor description error corrected july 15, 2002 preliminary
1/4 inch vga cmos im age sensor s5k433ca, s5k433la 3 introduction the s5k433ca and s5k433la are highly integrated single chip cmos image sensors fabricated by samsung 0.35 m m cmos image sensor p rocess technology. it is developed for imag ing application to realize high - efficiency and low - power photo sensor. the sensor has 640 x 480 effective pixels with 1/4 inch optical format. the sensor has on - chip 10 - bit adc blocks to digitize the pixel output and also on - chip cds to reduce fixed pattern noise (fpn) drastically. with its few interface signals and 10 - bit raw data directly connected to the external devices, a camera system can be configured easily. s5k433ca is suitable for a camera system with st andard 3.3v logic operation and s5k433la is suitable for low power camera module with 2.8v power supply. features ? process technology: 0.35 m m dptm cmos ? optical size: 1/4 inch ? unit pixel: 5.6 m m x 5.6 m m ? effective resolution: 640x480, vga ? line progressive r ead out. ? 10 - bit raw image data output ? programmable exposure time ? programmable gain control ? auto dark level compensation ? windowing and panning ? sub - s ampling (2x, 3x, 4x) ? standby - mode for power saving ? maximum 36 frame per second ? bad pixel replacement ? single power supply voltage: 3.3v or 2.8v ? package type: 48 - clcc/plcc products product code power supply backend process description s5k433ca01 3.3 v s5k433la01 2.8 v none monochrome image sensor s5k433ca02 3.3 v S5K433LA02 2.8 v on - chip micro lens high sensitivi ty monochrome image sensor s5k433ca03 3.3 v s5k433la03 2.8 v on - chip color filter and micro lens rgb color image sensor
s5k433ca, s5k433la 1/4 ? vga cmos image sens or 4 block diagram figure 1. block diagram timing generator rstn stbyn mclk vsync hsync dclk scl sda main clock divider i 2 c interface control registers active pixel sensor array row driver even column cds odd column cds 10 - bit column adc 10 - bit column adc vddd vssd vddio vssio vdda vssa post processing data9 data8 data7 data6 data5 data4 data3 data2 data1 data0
1/4 inch vga cmos im age sensor s5k433ca, s5k433la 5 pixel array (top view on chip. d isplayed image will be flipped.) figure 2. pixel array configuration (14,14) read out start point active pixel s optical black pixel s (0,0) default window of interest 640x480 10 4 r b g g 8 6 r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g 8 6 3 0 4 r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g r b g g
s5k433ca, s5k433la 1/4 ? vga cmos image sens or 6 pin configuration figure 3. pin configuration 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 6 5 4 3 2 1 48 47 46 45 44 43 31 32 33 34 35 36 37 38 39 40 41 42 (nc) (nc) data8 data7 data6 data5 data4 data3 data2 data1 (nc) (nc) stbyn vbba vssa vdda vssio (nc) (nc) vddio vdda vssa vbba test2 data0 (nc) vdda vssa vbba vssd (nc) vssio mclk scl sda rstn data9 (nc) vdda vssa vbba vddd (nc) vddio dclk hsync vsync test1 first readout pixel
1/4 inch vga cmos im age sensor s5k433ca, s5k433la 7 maximum absolute lim it characteri stic symbol value unit operating voltage (vddd, vddio, vdda supply relative to vssd, vssio, vssa, vbba) v dd - 0.3 to 3.8 v input voltage v in - 0.3 to v dd +0.3 (max. 3.8) operating temperature t opr - 2 0 to + 60 storage temperature t stg - 40 to +1 25 (1) c - 40 to +85 (2) notes: 1. the maximum allowed storage temperature for s5k433c(l)x01. 2. the maximum allowed storage temperature for s5k433c(l)x02 and s5k433c(l)x03.
s5k433ca, s5k433la 1/4 ? vga cmos image sens or 8 electrical character istics dc characteristics ( t a = - 2 0 to + 60 c, c l = 15pf) characteristics symbol condition min typ max unit operating voltage v dd vddd, vddio, s5k433ca 3.0 3.3 3 . 6 v vdda s5k433la 2.55 2.8 3.05 input voltage (1) v ih - 0.8v dd - - v il - 0 - 0.2v dd input leakage current ( 2 ) i il v in = v dd to v ss - 1 0 - 1 0 m a input leakage current with pull - down ( 3 ) i il d v in = v dd 1 0 30 60 high level output v oh i oh = - 1 m a v dd - 0. 05 - - v voltage ( 4 ) i oh = - 4m a s5k433ca 2.4 - - s5k433la 1.9 - - low level o utput v ol i o l = 1 m a - - 0.05 voltage ( 5 ) i ol = 4ma - - 0.4 high - z output leakage current ( 6 ) i o z v o ut = v dd - - 10 m a supply current i stb stbyn=low(active) all input clocks = low - - 10 m a i dd f mclk = 24.54 mhz v dd = 3.3 v ( 7 ) - 27 - ma 0 lux ill umination v dd = 2. 8 v ( 8 ) - 18 - notes: 1. applied to mclk, rstn, stbyn, scl, sda, test1, test2 pin. 2. mclk, rstn, stbyn, scl, sda pin 3. test1, test2 pin 4. dclk, hsync, vsync, data0 to data9 pin 5. dclk, hsync, vsync, data0 to data9, scl, sda pin 6. sd a pin when in high - z output state 7. s5k433ca 8 . s5k433la
1/4 inch vga cmos im age sensor s5k433ca, s5k433la 9 imaging characteristics (light source with 3200k of color temperature and ir cut filter (cm - 500s, 1mm thickness) is used. electrical o perating conditions follow the recommended typ ical values . the control registers are set to the default values . t a = 25 c if not specified. ) notes: 1. measured minimum output level at 100 lux illumination for exposure time 1/30 sec. 7x7 rank filter is applied for the whole pixel area to eliminate the values from defective pixels. 2. measured average output at 25% of saturation level illumination for exposure time 1/30 sec. green channel output values are used for color version. 3. measured average output at zero illumination without any offset compensation for exposure time 1/30 sec. 4. 20 log (saturation level/ dark level rms noise excluding fixed pattern noise). 60db is limited by 10 - bit adc. 5. 20 log ( average output level /rms noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure time 1/30 sec. 6. difference between maximum and m inimum p ixel output level s at zero illumination for exposure time 1/30 sec. 7x7 median filter is applied for the whole pixel area to eliminate the values from defective pixels. 7, difference between maximum and minimum p ixel output level s divided by averag e output level at 25% of saturation level illumination for exposure time 1/30 sec. 7x7 median filter is applied for the whole pixel area to eliminate the values from defective pixels. 8. for the column - averaged pixel output values, maximum relative deviati on of values from 7 - depth median filtered values for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec. 9. for the row - averaged pixel output values, maximum relative deviation of values from 7 - depth median filtered va lues for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec. characteristic symbol condition min typ max unit saturation level (1) v sat s5k433ca 950 1000 - mv s5k433la 850 900 - sensit ivity (2) s s5k433(c,l)x01 - 1500 - mv/lux sec s5k433(c,l)x02 - 4000 - s5k433(c,l)x03 - 1500 - dark level (3) v dark t a = 40 c - 9 18 mv/sec t a = 60 c - 50 100 dynamic range (4) dr - 60 - db signal to noise ratio (5) s/n - 40 - dark signal non - uniformity (6) dsnu t a = 60 c - - 100 mv/sec photo response non - uniformity (7) prnu - 4 8 % vertical fixed pattern noise (8) vfpn 4 8 % horizontal fixed patte rn noise (9) hfpn 4 8 %
s5k433ca, s5k433la 1/4 ? vga cmos image sens or 10 ac characteristics (v dd = 3.0v to 3.6v for s5k433ca, v dd = 2.55v to 3.05v for s5k433la, ta = - 2 0 to + 60 c , c l = 50 pf) notes: 1. 8 - bit adc resolution case. if 10 - bit adc resolution is used, the frequency should be over 12mhz. 2. the period time of main input clock, mclk . characteristic symbol condition min typ max unit main input clock frequency f mclk duty = 50% 3 (1) 24.54 30 mhz data output clock frequency f dclk - 2 12.27 15 propagation delay time t pdmd dclk output - - 20 ns from main input clock t pdmo data output - - 25 t pdmh hsync output - - 25 t pdmv vsync output - - 25 propagation delay time t p ddo data output - - 10 from data output clock t p dd h hsync output - - 10 t pddv vsync output - - 10 reset input pulse width t wrst rstn=low(ac tive) 5 - - t mclk (2) standby input pulse width t wstb stbyn=low(active) 4 - - t pdmd data mclk dclk 0.5v dd hsync vsync t pddo t pdmo t pdmd t pddh t pdmh t pddh t pdmh t pddv t pdmv
1/4 inch vga cmos im age sensor s5k433ca, s5k433la 11 i 2 c ser ial interface characteristics characteristic symbol condition min typ max unit clock frequency f sck - - - 400 khz clock high pulse width t w h scl 800 - - ns clock low pulse width t w l sc l 1000 - - clock rise/fall time t r /t f scl, sda - - 30 0 data set - up time t ds sda to scl 30 0 - - data hold time t dh sda to sc l 1200 - - start condition hold time t sth - 4 t mclk stop condition setup time t sts - 4 - - stop to new start gap t gss - 8 - - capacitance for each pin c pin scl, sda - - 4 pf capacitive bus load c bus scl, sda - - 200 pull - up resistor r pu scl, sda to v dd 1.5 - 10 k w sda scl 0.1v dd 0.9v dd t strs t strh t wl t dh t wh t ds t f t r 0.1v dd 0.9v dd t stps rstn stbyn t wstb t wrst mclk syst em reset partial power down complete power down
s5k433ca, s5k433la 1/4 ? vga cmos image sens or 12 pin description pin no i/o name function v ddd ( 24 ) power digital power supply for logical circuit ( v dd 10% ) v ssd ( 1 ) power 0v (gnd) v ddio ( 26, 35 ) power i/o power supply for i/o circuit ( v dd 10% ) v ssio ( 47, 38 ) power 0v (gnd) v dda ( 4, 21, 34, 39 ) power analog power supply for analog circuit ( v dd 10% ) v ssa ( 3, 22, 33, 40 ) power 0v (gnd) v bba ( 2, 23, 32, 41 ) power for analog circuit bulk bias ( 0v) mclk ( 4 6) i master clock master clock pulse input for all timing generators. rstn (43) i reset initializing all the device registers. (active low) stbyn (4 2 ) i standby activating power saving mode. ( high=normal operation, low=power saving mode ) data0~data9 ( 6, 9~16, 19 ) o image data output 10 - bit image data outputs. when adc resolution is reduced, the unused lower bits are set to 0. dclk ( 27 ) o data clock i mage data output synchronizing pulse output . hsync (28) o horizontal sync clock horizontal synchronizing pulse or data valid signal output . vsync (29) o vertical sync clock vertical synchronizing pulse or line valid signal output. scl (45) i serial inte rface clock i2c serial interface clock input sda (44) i/o serial interface data i2c serial interface data bus (external pull - up resistor required) test1 (30) i test input 1 test input signal. though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins. test2 (31) i test input 2 test input signal. though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins.
1/4 inch vga cmos im age sensor s5k433ca, s5k433la 13 control registers address (hex) reset value bits mnemonic description [5] bprm bad pixel replacement mode 0b: disabled (default), 1b: enabled [4] dlcm dark level compensation mode 0b: manual (default), 1b: auto [3] ccsm color channel separation mode 0b: not separated (default), 1b: se parated [2] shutc electronic shutter mode 0b: disabled (default), 1b: enabled 00h 02h [1:0] adcres adc resolution 00b: 8 - bit, 01b: 9 - bit, 10b: 10 - bit (default) [7] mircv vertical mirror control 0b: normal (default), 1b: mirrored [6] mirch horizon tal mirror control 0b: normal (default), 1b: mirrored [5:4] mcdiv main clock divider 00b: dclk=mclk, 01b: dclk=mclk ? 2 (default) 10b: dclk=mclk ? 4, 11b: dclk=mclk ? 8 [3:2] subsr row subsampling mode 00b: disabled (default), 01b: 2x, 10b: 3x, 11b: 4x 01h 10h [1:0] subsc column subsampling mode 00b: disabled (default), 01b: 2x, 10b: 3x, 11b: 4x 02h 00h [0] wrp_high 03h 0eh [7:0] wrp_low row start point for window of interest wrp[8:0] = 14d(default) 04h 00h [0] wcp_high 05h 0eh [7:0] wcp_low column start point for window of in terest wcp[8:0] = 14d(default) 06h 01h [0] wrd_high 07h e0h [7:0] wrd_low row depth for window of interest wrd[8:0] = 480d(default) 08h 02h [1:0] wcw_high 09h 80h [7: 0] wcw_low column width for window of interest wcw[9:0] = 640d(default) 0ah 80h [7:0] (factory use only))
s5k433ca, s5k433la 1/4 ? vga cmos image sens or 14 address (hex) reset value bits mnemonic description [4] [3] 0bh 02h [2:0] 0ch 0dh [7:0] (factory use only) 0dh 01h [4:0] cintr_high 0eh 06h [7:0] cintr_low row - step integration time in continuous frame capture mod e cintr[12:0] = 262d (default) 0fh 00h [5:0] cintc_high 10h 00h [7:0] cintc_low column - step integration time in continuous frame capture mode cintc[13:0] = 0d (default) 11h 01h [7:0] vswd vsync width vswd[7:0] = 1d (default) [5] vspolar vsync polarity 0: active high (default), 1: active low [4] vsdisp vsync display mode 0: sync mode (default), 1: data valid mode 12h 00h [1:0] vsstrt_high 13h 00h [7:0] vsstrt_low vsync start position vsstrt[9:0] = 0d (default) 14h 00h [4:0] vblank_high 15h 2dh [7:0] vblank_low vertical blank depth vblank[12 :0] = 45d (default) 16h 20h [7:0] hswd hsync width hswd[7:0] = 32d (default) [5] hspolar hsync polarity 0: active high (default), 1: active low [4] hsdisp hsync display mode 0: sync mode (default), 1: data valid mode 17h 00h [1:0] hsstart_high 18h 00h [7:0] hsstart_low hsync start position hsstrt[9:0] = 0d (default) 19h 00h [5:0] hblank_high 1ah 8ch [7:0] hblank_low horizontal blank depth hblank[13 :0] = 140d (default)
1/4 inch vga cmos im age sensor s5k433ca, s5k433la 15 address (hex) reset value bits mnemonic description [3:0] sgg1 1 st quadrisectional global gain sgg1[3:0] = 7d (default) 1bh 77h [7:4] sgg2 2 nd quadrisectional global gain sgg2[3:0] = 7d (default) [3:0] sgg3 3 rd quadrisectional global gain sg g3[3:0] = 7d (default) 1ch 77h [7:4] sgg4 4 th quadrisectional global gain sgg4[3:0] = 7d (default) 1dh 00h [6:0] pgcr red channel gain pgcr[6:0] = 0d (default) 1eh 00h [6:0] pgcg1 green(red row) channel gain or all channel gain ( ccsm =0) pgcg1[6:0] = 0d (defa ult) 1fh 00h [6:0] pgcg2 green(blue row) channel gain pgcg2[6:0] = 0d (default) 20h 00h [6:0] pgcb blue channel gain pgcb[6:0] = 0d (default) 21h 80h [7:0] offsr red channel analog offset offsr[7:0] = 128 (default) 22h 80h [7:0] offsg1 green(red row ) channel analog offset or all channel offset ( ccsm =0) offsg1[7:0] = 128 (default) 23h 80h [7:0] offsg2 green(blue row) channel analog offset offsg2[7:0] = 128 (default) 24h 80h [7:0] offsb blue channel analog offset offsb[7:0] = 128 (default) 25h 14h [6:0] pthresh bad pixel threshold pthresh[6:0] = 20d (default) 26h 00h [7:0] adcoffs adc offset adcoffs[7:0] = 0d (default) [5] - (factory use only) [4] - (factory use only) 27h 01h [3:0] p12stp (factory use only) p12 start control
s5k433ca, s5k433la 1/4 ? vga cmos image sens or 16 address (he x) reset value bits mnemonic description [7:5] - (factory use only) - 28h 40h [4:0] - (factory use only) - 29h 00h [7:0] - (factory use only) - 2ah 00h [7:0 ] blank blank register for general purpose [5] - (factory use only) [4] - (factor y use only) [3] - (factory use only) [2] - (factory use only) [1] - (factory use only) 2bh 02h [0] - (factory use only)
1/4 inch vga cmos im age sensor s5k433ca, s5k433la 17 operation descriptio n 1. output data format 1 - 1. main clock divider all the data output and sync signals are synchron ized to data clock output ( dclk ). it is generated by dividing the input main clock ( mclk ). the dividing ratio is 1, 2, 4, and 8 according to main clock dividing control register ( mcdiv ). for 10 - bit adc and vga resolution, dividing ratio of more than 2 is required. if ratio of 1 is used, the duty must be within 40% to 60%. 1 - 2. synchronous signal output the horizontal sync( hsync ) and vertical sync( vsync ) signals are also available. the sync pulse width, polarity and position are programmable by control r egisters (ref. timing chart). when display mode is enabled, the sync signal outputs indicate that the output data is valid ( hsdisp =1) or the output rows are valid ( vsdisp =1). 1 - 3 . window of interest control window of interest (woi) is defined as the pixel address range to be read out. the woi can be assigned anywhere on the pixel array. it is composed of four values: row start pointer( wrp ), column start pointer( wcp ), row depth( wrd ) and column width( wcw ). each value can be programmed by control registers . f or convenience of color signal processing, wcp is truncated to even numbers so that the starting data of each line is the red and green column of bayer pattern. figure 4 refers to a pictorial representation of the woi on the displayed pixel image. figure 4 . woi definition. 1 - 4 . vertical mirror and horizontal mirror mode control the pixel data are read out from left to right in horizontal direction and from top to bottom in vertical direction normally. by changing the mirror mode, the read - out sequence can be reversed and the resulting image can be flipped like a mirror image. pixel data are read out from right to left in horizontal mirror mode and from bottom to top in vertical mirror mode. the horizontal and the vertical mirror mode can programmed by hori zontal mirror control register ( mirch ) and vertical mirror control register ( mircv ). 1 - 5 . sub - sampling control the user can read out the pixel data in sub - sampling rate in both horizontal and vertical direction. sub - sampling can be done in four rates : ful l, 1/2, 1/ 3 and 1/ 4 . the user controls the sub - sampling using the sub - sampling control registers, subsr and subsc . the sub - sampling is performed only in the bayer space. window of interest ( wcp , wrp ) wcw wrd 0 687 507 0
s5k433ca, s5k433la 1/4 ? vga cmos image sens or 18 figure 5 . bayer space sub - sampling examples 1 - 6 . line rate and frame rate control ( virtual frame) the line rate and the frame rate can be changeable by varying the size of virtual frame. the virtual frame?s width and depth are controlled by effective woi and blank depths. the effective woi is scaled by the sub - sampling factors from woi set by register values. for cds and adc function, the virtual column width must be larger than ( adcres +1)* 256/(2^ mcdiv )+200 , where adcres is the adc resolution control register value. the horizontal and vertical blanking time ( hblank , vblank ) should be ov er 60 and 4, respectively. the resulting frame time and line time which are inverse of frame rate and line rate are represented by following equations: 1 frame time = { wrd / ( subsr +1) + vblank } * (1 line time) 1 line time = { w cw / ( s ubsc + 1) + hblank } * ( dclk period) 1 - 7 . c ontinuous f rame c apture m ode(cfcm) integration time control (electronic shutter control) in cfcm operation, the integration time is controlled by shutter operation. the shutter operation is done when shutter contr ol register ( shutc ) is set to ?1?. in shutter operation, the integration time is determined by the row step integration time control register( cintr ) and column step integration time control register( cintc ). the resulting integration time is expressed as; integration time = { tbd } where cintr = 0 to {tbd} , cintc = 0 to {tbd} . 1 - 8 . s ingle f rame c apture m ode(sfcm) integration time control to capture a still image, sfcm can be set by single frame capture enable register( sfcen ). there ar e two types of integration mode are implemented. in the rolling shutter mode ( sfcim =0), the integration time is controlled by sfcm integration time register ( sint ). the light integration period for each rows progresses with reading rows. the integration ti me is expressed as : integration time = sint * ( 1 line time ) subsr =01b, subsc =01b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b subsr =00b, subsc =1 1 b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b
1/4 inch vga cmos im age sensor s5k433ca, s5k433la 19 2. analog to digital converter ( adc) the image sensor has on - chip adc. two - channel column parallel adc scheme is used for separated color channel gain and offset control. 2 - 1. ad c resolution the default value of adc resolution is 10bit and can be change d to 8bit or 9bit by control the adc resolution control r egister ( adcres ) . lowering adc resolution reduces the required minimum line time . when the number of effective output bits i s reduced, upper n - bits of output ports are valid and lower bits always has value of ?0?. 2 - 2. correlated double sampling ( cds ) the analog output signal of each pixel includes some temporal random noise caused by the pixel reset action and some fixed pattern noise by the in - pixel amplifier offset deviation. to eliminate those noise components, a correlated double sampling(cds) circuit is used before converting to digital. the output signal sampled twice, once for the reset level and once for the actua l signal level sampling. 2 - 3. programmable gain and offset control the user can controls the gain of individual color channel by the programmable gain control registers ( pgcr , pgcg1 , pgcg2 , pgcb ) and offset by offset control registers ( offsr , offsg1 , o ffsg2 , offsb ) . if the color channel separation mode is disabled ( ccsm =0), pgcg1 and offsg1 change the gains and offsets for all channels. as increasing the gain control register, the adc conversion input range decreases and the gain increased as following equation: channel gain = 128 / (128 ? programmable gain control register v alue[6:0]) figure 6. relative channel gain r g1 g2 b r g1 g2 b r g1 g2 b r g1 g2 b 0 5 10 15 20 25 30 35 40 45 0 16 32 48 64 80 96 112 128 programmable gain control channel gain (db) 1 2 3 4 5 6 7 8 9 10 0 16 32 48 64 80 96 112 128 programmable gain control relative channel gain
s5k433ca, s5k433la 1/4 ? vga cmos image sens or 20 2 - 4. quad ris ectional global gain control the user can controls the global gain to change the gain for all color channel s by the global gain control registers ( sgg1 , sgg2 , sgg3 , sgg4 ). the global gain control register is composed of four register groups and each register value decides the gain for each quarter section of output code level. global gain = ( sgg [3:0]+1) / 8 figure 7. relative global gain the adc gain is dependent on mclk frequency (not on dclk frequency) and adc resolution. the default global gain is set for typical mclk frequency (24mhz) and 10 - bit adc. when the frequency and adc resolution is changed, the average global gain, ( sgg1 + sgg2 + sgg3 + sgg4 +4)/32 should be changed to maintain the resulting gain over unity for assuring appropriate adc conversion range. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 mclk frequency (mhz) minimum glabal gain 10-bit adc resolution 9-bit adc resolution 8-bit adc resolution figure 8. recommended minimum global gain control value 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 2 4 6 8 10 12 14 16 programmable gain control relative global gain -20 -15 -10 -5 0 5 10 0 2 4 6 8 10 12 14 16 programmable gain control glabal gain (db)
1/4 inch vga cmos im age sensor s5k433ca, s5k433la 21 by appro priately programming these four register values, the different output resolution according to the signal can be achieved and the intra - scene dynamic range can be increased by 16 times. in another application, the sectional global gain control can be used a s a rough gamma correction with four sectional linear approximation curve as shown in figure 9 . figure 9. quadrisectional glabal gain control 3. post processing 3 - 1. dark level compensation the d ark l evel of image sensor is defined as average output level without illumination. it includes pixel output caused by leakage current of the photodiodes and adc offset . to compensate the dark level, the output level of optical black(ob) pixels can be a good reference value. when auto dark level compensation regist er ( dlcm ) is set, the image sensor detects the ob pixel level at the start of every frame and analog - to - digital conversion range is shifted to compensate the dark level for that frame. so, the resulting output data of that frame will be almost zero under d ark state. if user wants the dark level which is not zero, the adc offset register ( adcoffs ) can be used. the lower 7 - bit value represent the offset value in output code for compensation and the msb is the sign to define whether the offset is positive ( ad coffs [7]=0) or negative ( adcoffs [7]=1). when not in auto dark level compensation mode, the adcoffs [7:0] act as a output code value to subtract the output image data. please notify that the all the 8 - bit data are used for an offset value without sign bit. 3 - 2. bad pixel replacement when the bad pixel replacement register ( bprm ) is enabled, the image sensor check that the image data is less or greater than horizontally neighboring pixels in same color channel by the preset threshold value ( pthresh ). if satis fied, the output of the pixel is replaced by the averaged value of the neighboring two pixels. the detectable defected pixels are rare and the bad pixel replacement action can remove defected image effectively. but it reduces the line resolution in horizon tal direction. 255 0 511 767 1023 adc output code at 10 - bit resolution sgg1=1111b sgg2=0111b sgg3=0011b sgg4=0000b adc input signal sgg1= 0 111b sgg2=0111b sgg3=0111b sgg4=0111b sgg 1 sgg2 sgg 3 sgg 4
s5k433ca, s5k433la 1/4 ? vga cmos image sens or 22 4 . i 2 c serial interface the i 2 c is an industry standard serial interface. the i 2 c contains a serial two - wire half duplex interface that features bi - directional operation, master or slave mode. the general sda and scl are the bi - direction al data and clock pins, respectively. these pins are open - drain type ports and will require a pull - up resistor to vdd. the image sensor operates in salve mode only and the scl is input only. the i 2 c bus interface is composed of following parts : start sign al, 7 - bit slave device address (0010001b) transmission followed by a read/write bit, an acknowledgement signal from the slave, 8 - bit data transfer followed by an acknowledgement signal and stop signal. the sda bus line may only be changed while scl is low. the data on the sda bus line is valid on the high - to - low transition of scl . figure 10. i 2 c bus write cycle figure 11. i 2 c bus read cycle sda s tart d7 d6 d5 scl ?0 ?0 ?1 ?0 ?0 ?0 ?1 i 2 c bus address i2c register address w rite a ck a ck sda scl d7 d6 d5 d4 d3 d2 d1 d0 data to w rite s top a ck d 4 d 5 d 2 d 1 d 0 sda s tart d7 d6 d5 scl ?0 ?0 ?1 ?0 ?0 ?0 ?1 i 2 c bus address i 2c register address w rite a ck a ck s top d 4 d 5 d 2 d 1 d 0 x sda re - s tart d7 d6 d5 scl ?0 ?0 ?1 ?0 ?0 ?0 ?1 i 2 c bus address data to be read read a ck a ck d 4 d 5 d 2 d 1 d 0
1/4 inch vga cmos im age sensor s5k433ca, s5k433la 23 timing chart vertical timing diag ram continuous frame capture mode ( default case ) ( delayed ver tical sync case) ( vertical data valid mode case) vsdisp=1 hsync wrd (480 rows) 1 frame = wrd + vblank ( 525 rows ) wrp (14th row) vsync vswd (1row) rows data vblank (45 rows ) hsync 1 frame = wrd + vblank vsync vsstrt data hsync (hsdisp=0) wrd vsync data vblank 2 rows vswd 2 rows hsync (hsdisp=1)
s5k433ca, s5k433la 1/4 ? vga cmos image sens or 24 horizontal timing di agram ( default case ) ( delayed horizontal sync case ) ( hor izontal data valid mode case ) hsdisp=1 w cw ( 640 columns ) 1 row = wcw + hblank ( 780 column s ) hswd ( 32 d clk ) hbla nk ( 140 columns ) hsync vsync data d clk 10 d clk wcp ( 14th column) w cw 1 row = wcw + hblank hsstrt hsync vsync data d clk hswd 42 d clk 42 d clk w cw hsync vsync data d clk 42 d clk hblank
1/4 inch vga cmos im age sensor s5k433ca, s5k433la 25 package dimension bottom vi ew side view top view center of image area (x= + 0. 50 0.15, y=0. 00 0.15 from package center) max. chip rotation = 1.5 degree max. chip tilt = 0.05mm 0.5 1 0.0 8 r 0.1 5 4 corners 48 1 1.016 0.18 1 1 . 176 0.1 3 1.016 0.0 8 1.65 0.1 8 0.55 0.05 glass 6 43 48 1 7 18 19 3 0 42 3 1 1 4 .2 2 sq +0.30/ - 0.13 48pin clcc

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